A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to utilize vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array includes vertical memory strings extending through openings in tiers of conductive structures (e.g., word lines, control gates) and dielectric materials at each junction of the vertical memory strings and the conductive structures. Such a configuration permits a greater number of switching devices (e.g., transistors) to be located in a unit of die area (i.e., length and width of active surface consumed) by building the array upwards (e.g., longitudinally, vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors.
In a conventional 3D memory device structure, data lines (e.g., bit lines, digit lines) are electrically coupled to vertical memory strings of a vertical memory array, and an opening is provided next to edges of the vertical memory array to accommodate data line contacts for each of the data lines. The data line contacts electrically couple the data lines to control logic circuitry to facilitate operations (e.g., read operations, write operations, erase operations) on the vertical memory strings of the vertical memory array. However, providing the opening for the data line contacts next to the vertical memory array can effectuate damage to and/or defects at the edges of the vertical memory array (e.g., commonly referred to as “array edge effects”). Accordingly, an array of “dummy” pillars (e.g., dielectric pillars) is conventionally provided between the vertical memory array and the opening to set the edges of the vertical memory array back farther from the opening and mitigate the aforementioned damage to and/or defects at the edges of the vertical memory array. Unfortunately, the area conventionally required for such an opening and such an array of dummy pillars can frustrate improvements in overall lateral dimensions and packing density in such 3D memory device structures.
Accordingly, there is a need for 3D semiconductor device structures exhibiting improved packing density, such as memory device structures for 3D non-volatile memory devices (e.g., 3D NAND Flash memory devices), as well as for associated semiconductor devices and electronic systems including the semiconductor device structures.